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SC1
6
C850
Al
li
n
for
m
at
ion
pr
ovi
ded
in
this
do
cum
ent
i
s
sub
jec
tto
leg
a
ld
is
c
la
im
er
s.
NXP
B.V
.
2010.
Al
lr
ig
h
ts
re
s
e
rv
ed.
Produ
ct
d
a
ta
sheet
R
e
v
.2
—
1
N
o
vem
ber
2010
21
o
f55
N
X
P
Semi
conductor
s
SC16C850
2
.5
to
3.3
V
UART
with
1
28-
byt
e
FIFOs
and
IrDA
e
n
cod
e
r/dec
ode
r
Table 8.
SC16C850 internal registers
A2 A1 A0 Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
0
RHR
0xXX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R
0
THR
0xXX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W
0
1
IER
0x00
CTS
RTS
Xoff
Sleep
modem
status
interrupt
receive line
status
interrupt
transmit
holding
register
interrupt
receive
holding
register
interrupt
R/W
0
1
0
FCR
0x00
RCVR
trigger
(MSB)
RCVR
trigger (LSB)
TX trigger
TX trigger
reserved
XMIT FIFO
reset
RCVR FIFO
reset
FIFOs
enable
W
0
1
0
ISR
0x01
FIFOs
enabled
FIFOs
enabled
INT priority
bit 4
INT priority
bit 3
INT priority
bit 2
INT priority
bit 1
INT priority
bit 0
INT status
R
0
1
LCR
0x00
divisor latch
enable
set break
set parity
even parity
parity
enable
stop bits
word length
bit 1
word length
bit 0
R/W
1
0
MCR
0x00
clock
IrDA enable
INT type
loopback
OP2
OP1
RTS
DTR
R/W
1
0
1
LSR
0x60
FIFO data
error
THR and
TSR empty
THR empty
break
interrupt
framing
error
parity error
overrun
error
receive data
ready
R
1
0
1
EFCR
0x00
reserved
Enable extra
feature bit 1
Enable extra
feature bit 0
Enable
TXLVLCNT/
RXLVLCNT
W
1
0
MSR
0xX0
CD
RI
DSR
CTS
ΔCD
ΔRI
ΔDSR
ΔCTS
R
1
SPR
0xFF
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
0
DLL
0xXX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
0
1
DLM
0xXX
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
Second special register set[6] 0
1
TXLVLCNT
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R
1
0
RXLVLCNT
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R